1. Field of the Invention
The present invention relates to a clock and data recovery circuit and method capable of generating clock signals that are synchronized with received data.
2. Description of the Related Art
Universal Serial Bus (USB) is an interface standard for data transmission between a computer and its peripheral devices. For data communication between a computer and a peripheral device according to the USB interface standard, there are several requirements. For example, a computer and a peripheral device must have a USB transmission unit and a USB receiving unit therein, respectively. Also, a clock signal is not transmitted between the USB transmission unit and the USB receiving unit. Instead, only Non-Return-to-Zero (NRZ) or Non-Return-to-Zero-Inverted (NRZI) data is transmitted between the USB transmission unit and the USB receiving unit. Accordingly, a clock signal is recovered in the USB receiving unit using the received data.
Generally, the USB transmission unit and the USB receiving unit use the same clock signal, so the clock signal used by the USB transmission unit usually has the same frequency as the clock signal used by the USB receiving unit but has a different phase. Typically, the USB receiving unit has a clock and data recovery circuit for recovering the clock signal having the same frequency and phase as the clock signal used by the USB transmission unit, and generates a recovered clock signal that is synchronized with the received data.
FIG. 1 illustrates an example of a clock and data recovery circuit, in accordance with the present invention. Referring to FIG. 1, a conventional clock and data recovery circuit comprises a phase detector 10, a bi-directional shift register 12, a phase selector 14, a clock generator 16 and a multi-phase clock generator 18.
The phase detector 10 generates a down signal DN when received data RDATA leads a recovered clock signal RCCK in phase, and generates an up signal UP when the received data lags the recovered clock signal RCCK in phase, after comparing the phases of the received data RDATA and the recovered clock signal RCCK. The bi-directional shift register 12 counts down in response to the down signal DN and counts up in response to the up signal UP, and generates a control signal CON. The phase selector 14 selects one clock signal from a plurality of clock signals P1, P2, P3, . . . , Pn output from the multi-phase clock generator 18, and outputs the selected clock signal as a recovered clock signal RCCK. The clock generator 16 generates a receiving clock signal RXCK. The multi-phase clock generator 18 receives the receiving clock signal RXCK, and generates n clock signals P1, P2, P3, . . . , Pn which have the same frequency and different phases from each other by as much as 360/N×K, wherein K is an integer between zero to N−1. If, N is 8, 8 clock signals are generated from the multi-phase clock generator 18, and the generated clock signals have phase differences from each other by as much as 45 degrees, so that the 8 clock signals have phases 0, 45, 90, 135, 180, 225, 270 and 315 degrees, respectively. The receiving clock signal RXCK generated by the clock generator 16 has the same frequency as a clock signal which is used in the USB transmission unit (not shown), for transmitting the received data RDATA.
FIG. 2 is a timing diagram showing the operation of the clock and data recovery circuit shown in FIG. 1.
First, the phase detector 10 compares the respective phases of the received data RDATA and the recovered clock signal RCCK. If an initial value of a control signal CON output from the bi-directional shift register is 1 and the phase selector 14 selects a clock signal CK0, the recovered clock signal RCCK is the clock signal CK0. Accordingly, at this time, the phase detector 10 generates an up signal UP because the received data lags the recovered clock signal in phase. Then, the bi-directional shift register 12 counts up and increments the value of the control signal to 2. The phase selector 14 generates a clock signal CK45 as the recovered clock signal RCCK in response to the incremented control signal CON having the value 2. The phase detector 10 again compares the phases of the received data RDATA and the recovered clock signal RCCK, and generates the up signal UP because the received data RDATA lags the recovered clock signal RCCK in phase. Then, the bi-directional shift register counts up and the value of the control signal CON increments to 3. Then, the phase selector 14 generates a clock signal CK90 as the recovered clock signal in response to the control signal CON. The phase detector 10 compares the phases of the received data RDATA and the recovered clock signal RCCK, and generates a down signal DN because the received data RDATA leads the recovered clock signal RCCK in phase. Then, the bi-directional shift register 12 counts down and decrements the value of the control signal CON to be 2.
In the manner described above, the clock and data recovery circuit shown in FIG. 1 generates the recovered clock signal in synchronization with the received data, and the clock signal CK45 and the clock signal CK90 are alternately generated as the recovered clock signal RCCK.
Accordingly, the clock and data recovery circuit in accordance with the conventional art is limited in that it does not generate the recovered clock signal RCCK in precise synchronization with the received data RDATA. Also, the conventional art is limited in that it requires a maximum of N clock periods in order to generate the recovered clock signal RCCK in relative synchronization with the received data.
If the N is set to a small number to synchronize the received data RDATA with the recovered clock signal RCCK within a short period, the phase difference between the received data RDATA and the recovered clock signal RCCK becomes greater even though the received data RDATA and the recovered clock signal RCCK are synchronized.